1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a first semiconductor layer formed on a substrate via an embedded insulation film and an FBC (Floating Body Cell) for storing majority carriers in a floating channel body formed in the first semiconductor layer and thereby storing data.
2. Related Art
It may become difficult to fabricate a DRAM cell composed of a conventional one transistor and a trench capacitor or a stacked capacitor, as the DRAM cell becomes finer. As a memory cell that can be used instead of such a DRAM cell, a new memory cell FBC that stores majority carriers in a floating body of an FET formed on a SOI (Silicon on Insulator) or the like and thereby stores information has been proposed (See Japanese Patent Application Laid-Open Publication Nos. 2003-68877 and 2002-246571).
First, the principle of FBC writing and reading will now be described by taking an N type MISFET as an example. The state in which there are a large number of holes in the channel body is defined as “1”, and the state in which there are a small number of holes in the channel body is defined as “0”. The FBC includes an n-FET formed on a SOI substrate. The FBC is connected at its source to GND (0 V), connected at its drain to a bit line (BL), and connected at its gate to a word line (WL). The channel body of the FBC is electrically floating.
For writing “1”, the transistor is operated in the saturation state. For example, the word line WL is biased to 1.5 V and the bit line BL is biased to 1.5 V. In such a state, a large number of electron-hole pairs are generated near the drain by impact ionization. Among them, electrons are absorbed to the drain terminal, but holes are stored in the channel body having a low potential.
In a state in which a current of holes generated by impact ionization balances a forward current of a pn junction between the channel body and the source, the channel body voltage arrives at the equilibrium state. The channel body voltage is approximately 0.7 V.
On the other hand, for writing “0” data, the bit line BL is pulled down to a negative voltage, for example, to −1.5 V. The channel body formed of a p-region and an n-region connected to the bit line BL are biased largely in the forward direction by the operation, and most of the holes stored in the channel body are emitted into the n-region. The state in which the number of holes in the channel body has decreased is “0”.
For reading data, for example, the word line WL is set equal to 1.5V and the bit line is set equal to 0.2V to cause the transistor operate in the linear region. By using the effect (body effect) that the threshold voltage Vth of the transistor differs due to difference in the number of holes stored in the channel body, the current difference is sensed to discriminate “1” and “0”.
The reason why the bit line voltage is set to a low value (for example, to 0.2 V) when reading data is as follows: if the bit line voltage is set higher and the transistor is biased into the saturation state, there is a likelihood that the data may be disguised as “1” by impact ionization when reading “0” and “0” will not be able to be sensed correctly.
When reading data, the cell current flowing through the FBC is minute. In order to discriminate “1” and “0” accurately, therefore, typically a reference cell having the same structure as the FBC has is provided and a current difference between a cell current flowing through the FBC and a cell current flowing through the reference cell is sensed to discriminate “1” and “0” in data.
In some cases, however, the threshold value Vth in a large number of FBCs in the memory disperses largely due to parameter variations in the device fabrication process. For example, if the channel length L of the transistor in the FBC disperses, the threshold value Vth disperses largely due to the short channel effect. Furthermore, due to the dispersion in the channel width, the narrow channel effect works and the threshold value Vth disperses.
In the future, it is expected that dispersion in positions and the number of impurity atoms existing in the channel largely affects the characteristics of the transistor as the transistor becomes finer. Inevitably, there is a likelihood that the threshold value Vth may largely disperse.
If the dispersion in threshold value Vth exceeds a certain tolerance, it becomes difficult in the sense scheme using the reference cell as described above to discriminate data “1” and “0” accurately. The reason is as follows: if Vth in the FBC largely differs from Vth in the reference cell, both of the potential obtained at the sense node when the data is “1” and the potential obtained at the sense node when the data is “0” become higher or lower than the potential VREF at the reference node. Therefore, the data “1” and “0” cannot be discriminated accurately.
The following sense amplifier is also conceivable. In order to conduct comparison with the reference cell, a reference cell for data “1” and a reference cell for data “0” are provided. By using the average of cell currents flowing through the reference cells of the two kinds as a reference current, comparison with the cell current flowing through the FBC is conducted.
However, a reference word line connected to the reference cell for the data “1” and a reference word line connected to the reference cell for the data “0” become necessary, and the number of word lines in the cell array increases. This results in a problem that current consumption increases. In order to cope with the increase of the current consumption, the mirror ratio in a current mirror circuit in the sense amplifier must be set equal to 2 and the circuit area of the sense amplifier increases. In addition, as a major problem, unbalance in capacitance between the bit line and the reference bit line cannot be avoided and it becomes impossible in the dynamic sense scheme to sense data normally, if the reference cell for data “1” and the reference cell for data “0” are provided.
In the above-described conventional FBC, one bit is formed of one transistor. As compared with the conventional DRAM cell in which one bit is formed of one transistor and one capacitor, the cell area becomes small and the conventional FBC is advantageous for realizing a large capacity. However, there is a likelihood that the finer transistor technique will not be advanced unlike heretofore due to physical limits.